The present invention relates to a wiring substrate manufacturing technique and particularly relates to a technique effectively applied to a manufacturing method for a wiring substrate used in a semiconductor device.
A wiring substrate is described in, for example, Japanese Patent Laid-Open No. 9-321184. Japanese Patent Laid-Open No. 9-321184 discloses a connection substrate (wiring substrate) for connecting a high wiring density semiconductor chip to a low wiring density printed wiring substrate and a manufacturing technique thereof. This connection substrate consists of a photosensitive glass plate, and one wiring layer to which bumps of the semiconductor chip are connected is formed on the upper surface of the connection substrate. In addition, a plurality of bumps connected to electrodes of the printed wiring substrate are formed on the lower surface of the connection substrate. Wirings on the upper surface of the connection substrate are electrically connected to the bumps on the lower surface thereof, through via holes penetrating the upper and lower surfaces of the connection substrate. These via holes are formed by a photolithographic technique, and a conductor is embedded into each via hole by plating.
Also, a technique for forming microstructure via holes and wirings on a glass plate by using an exposure treatment of a photosensitive material with ultraviolet rays is disclosed by, for example, Japanese Patent Laid-Open No. 8-255981. According to Japanese Patent Laid-Open No. 8-255981, a shade film made of metal such as Ti, Cr, Al, Ni, W, Mo, Ta or Cu is formed on the glass plate, thereby preventing UV multiple reflection between the upper and lower surfaces of the glass plate during the exposure treatment for the photosensitive material. In addition, by setting the film thickness of the shade film made of one of the above-stated metal at not more than 3 μm, the thermal conductivity of the glass plate is improved.